Last application dateSep 30, 2023 00:00DepartmentTW05 – Department of Information TechnologyContractLimited durationDegreeMaster of Science in Electronics Engineering, Master of Science in Information and Communication TechnologyOccupancy rate100%Vacancy typeResearch staff
PhD researcher on real-time digital signal processing for distributed multi-user massive MIMO systems
To strengthen our design team, this vacancy is looking for a strong research profile on real-time digital signal processing for wireless applications on FPGA and ASIC in the context of distributed massive MIMO communication systems. This PhD candidate will work on algorithms, designs, system prototyping, and experiments for next generation radio access networks.
The Internet Technology & Data Science Lab (IDLab) is an imec research group at Ghent University and the University of Antwerp. IDLab focuses its research on internet technologies and data science. Within IDLAB, the Design team is internationally recognized as a leading research group on high-speed and high-frequency integrated circuits for next-generation communications systems. At this moment, the Design group is for example active in eight European projects and in direct research contracts with world-leading industry partners. Besides these high-profile projects, the Design group is also a core partner in the ERC Atto project of Prof. Piet Demeester. These roadmaps form the perfect basis for high-level and industry-relevant research in an environment with expert peers and top-notch test and measurement equipment.
The main research lines focus on wired (fiber-optic, radio-over-fiber, copper), wireless (RF, 5G-6G, mmWave) and instrumentation for which custom CMOS or SiGe BiCMOS chips are developed and integrated in (FPGA-based) system demonstrators.
Next generation wireless communication systems targeting industrial applications demand extremely high reliability. One of the ways to realize this is by deploying a very large number of remote radio nodes that cooperate together. However, this approach puts a very high load on the fronthaul network connecting these nodes: synchronization between different nodes should be very tight (a few degrees phase accuracy, 100 ps timing accuracy). The bandwidth of the system should remain controllable. The latter implies that part of the signal processing needs to be performed distributed in the fronthauling network. To address these challenges, the Design group is looking for PhD researchers to investigate novel scalable radio access architectures and real-time signal processing solutions.
- You need to hold a relevant master’s degree (e.g., Master of Science in Electronics Engineering, Master of Science in Information and Communication Technology, …) with demonstrated first-class performance (e.g., outstanding grades, thesis result, or publications).
- You can demonstrate mastery of the following core aspects:
- o Digital design skills: RTL design and knowledge of Verilog / VHDL.
- o Knowledge about wireless PHY, OFDM modulation and detection
- o Expertise on synthesis and place and routing and digital implementation tools such as Xilinx Vivado / Cadence Xrun / Candence Innovus are a plus.
- You are a team player with good networking and reporting skills.
We offer a fully funded PhD position to do full-time research in a highly international and friendly working environment, with a competitive salary at Ghent University. As a researcher you will publish and present your research results at major international conferences and in scientific journal in order to pursue your PhD degree.
Typical research projects in the Design group involve multiple researchers with different specialties working as a team, stimulating knowledge creation across different domains. Further, we offer the possibility to follow various advanced training courses in Belgium or abroad.
After initiation in the field, you will perform research on real-time signal processing algorithms which will be implemented and demonstrated on our distributed massive MIMO testbed, consisting at the moment of 64 synchronously interconnected antennas, high-end FPGAs. After verification in the testbed, implementation in the in-house developed fronthaul ASICs will be considered.
How to apply
Applications can be sent to prof. Guy Torfs (firstname.lastname@example.org) including a cover letter and CV. Suitable candidates will be invited for an interview and may get a small assignment. We offer you a flexible starting date, with a preference to start as soon as possible.